In a variety of circuits in which voltage changes are contaminated with switching transients or the like, deglitching circuits have been provided to eliminate the unwanted switching transients. A typical example of such deglitching circuit is contained in U.S. Pat. No. 3,869,085. That patent relates to a controlled current vector generator for cathode ray tube displays. As disclosed, a computer generates digital signals representing desired deflections for a cathode ray tube. A digital-to-analog converter converts the computer's digital output to analog form, a deglitching circuit is included connected between the output of the digital-to-analog converter and the cathode ray tube deflection system to prevent switching transients, or glitches, from reaching the deflection system of the cathode ray tube. Although the preferred embodiment of the invention to be disclosed hereinafter is also for use with a cathode ray tube system, deglitching circuits have wide application in other arrangements in which switching transients contaminate an analog signal level or level transition.
An ideal deglitching circuit is shown in FIG. 1, where a voltage source 10 is coupled to one terminal of a timed switch 12 whose other terminal is connected to the output, with a capacitor 13 connected between the other terminal of the switch 12 and ground. A timing control 14 controls the condition of the switch 12.
In one typical arrangement, source 10 is actually a digital-to-analog converter which exhibits high frequency voltage spikes in the output voltage occasioned by transients generated during the switching which takes place in the digital-to-analog converter. The ideal deglitching circuit of FIG. 1 is arranged to close the switch 12 after the digital-to-analog converter has settled to charge the capacitor 13 to the analog voltage. Just prior to the digital-to-analog converter changing its output, the timing control 14 opens the switch 12 and maintains the switch 12 in an open condition until the new value provided by the digital-to-analog converter has settled at which time the switch is again closed so that the capacitor 13 can be charged or discharged to a new potential.
Typically, the deglitching circuit requires rapid switch operation and requires that switch 12 does not capacitively couple transients into the output. In a typical arrangement employing digital clock rates of 2 mHz, the period between possible changes of the output of the digital-to-analog converter is 500 nanoseconds. A good digital-to-analog converter such as Analog Devices 1108 settles in current to within 0.05% of its steady state value in 60 nanoseconds. Converting this current signal to a voltage within some predetermined range can require 200 nanoseconds employing a 15 mHz. LM 118 monolithic operational amplifier. This leaves only 300 nanoseconds of the available 500 nanosecond period to close the switch, charge the capacitor to the new voltage and again open the switch. While field effect transistors are rapid switching devices they are unusable in this application because the gate voltage excursion is capacitively coupled into the output as another transient.
The referenced patent employs a diode bridge as the switch. When current passes through the bridge the diodes conduct allowing the digital-to-analog converter output to be connected to the buffer amplifier input. When bridge current is terminated the diode bridge appears as an open switch. Current sources and sinks steer current through the bridge. Inasmuch as the turn-on and turn-off times of the various current sources employed with the bridge are not equal, switching transients are coupled through to the output. While the switching transients are reduced over that which would have been available without use of the diode bridge as a switch, nevertheless, in certain applications these switching transients are disadvantageous.
Accordingly, it is an object of the present invention to provide a deglitching circuit with markedly reduced switching transients in the output. It is another object of the present invention to provide a deglitching circuit which is capable of the rapid operation required, for example, commensurate with 2 mHz. digital clock rates, and which at the same time, shows markedly reduced switching transients as compared to the deglitching circuit of the referenced patent.